1. Field of Invention
The present invention relates to the manufacture of high performance VLSI semiconductor chips in general and more particularly to a method of manufacturing planarized semiconductor chips having a plurality of levels of metallurgy, according to an improved stud vertical wiring technique which accommodates differences both in stud elevation and stud size.
A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wires. In VLSI chips these metal patterns are multi-layered and separated by layers of an insulating material. Interconnections between metal wiring patterns are made by holes (or via-holes), which are etched through the insulator. Typical chip designs consist of one or two wiring levels with three wiring levels being the current state-of-the-art technology. Circuit cost and performance continue to place demands on the fabrication processes in such a way that adding additional wiring levels can be competitive even though additional processing steps are required. Obviously, there comes a point in this evolutionary cycle where process architecture has to be changed to allow for circuit designs with ever increasing density requirements. That point appears to be the addition of a fourth level metal and the reduction of via holes to less than several microns.
The isotropic nature of most etchants results in a via hole that is larger than the image printed in the photoresist. This enlargement is called process bias. Process bias has a direct impact on circuit density since it uses up valuable real estate. Creating anisotropy in the formation of a via hole reduces bias and increases density. One process which has anisotropy is Reactive Ion Etching (RIE) with a dry plasma. While zero bias is possible with RIE, it is not practical because the via-hole formed would have vertical sidewalls and the subsequent metal deposition would result in open circuits due to the well known edge coverage problem.
Therefore, RIE processes are usually designed with some degree of process bias to taper the resulting via hole.
Reducing bias further can be accomplished by eliminating the via-hole and replacing it with a via stud or vertical wire, hereafter called a stud. The lift-off process is currently used to form the studs. While the use of the lift-off process has minimized process bias to much less than a micron, it is also required to produce a stud where there is no need for etch stops which would complicate the process. Therefore, it is possible to place studs directly on top of device contacts and eliminate the need for access wiring. In addition, it is also possible to begin thinking about "stacking" studs one on top of the other, to allow for electrical connection between metal wires or lands which are not on the same plane. In short, the replacement of via-hole technique, by the stud technique has produced a synergistic effect of not only reducing process bias to a minimum but also allows for a complete review of current wiring architecture.
In conclusion, studs have definite advantages compared to the via hole technique such as:
1. Multilevel wiring with four (or more levels of wires. PA1 2. Placing studs directly on device contacts without degrading the contact quality. PA1 3. Stacking a stud directly over one another. PA1 4. Planarized surfaces which allow upper levels of metal (2nd, 3rd, 4th, etc.) to have the same ground rules as the first level of metal. PA1 5. Reducing stud size below the current capability of an etched via. PA1 6. Maximize interlevel insulator thickness beyond current capabilities. PA1 1. U.S. Pat. No. 4,410,622 to Dalal et al granted Oct. 18, 1983, and assigned to the same assignee as the present invention. PA1 2. An article entitled "Integrated Stud for Multilevel Metal" by J. R. Kitcher published in the IBM Technical Disclosure Bulletin, Vol. 23, No. 4, September 1980, page 1395. PA1 3. An article entitled "RIE Process for Metal Wiring Using a Buried Mask" by J. R. Kitcher published in the IBM Technical Disclosure Bulletin, Vol. 23, No. 4, September 1980, page 1394. PA1 4. U.S. Pat. No. 3,801,880 to Harada et al granted Apr. 2, 1974. PA1 5. An article entitled "Dual Dielectric for Multilevel Metal" by T. A. Bartush published in the IBM Technical Disclosure Bulletin, Vol. 23, No. 9, February 1981, page 4140. PA1 6. U.S. Pat. No. 4,367,119 to Logan et al granted Jan. 4, 1983. PA1 7. U.S. Pat. No. 4,470,874 to Bartush et al. granted Sept. 11, 1984.
2. Prior Art
Because the vertical wiring stud technique has been demonstrated to be such a very powerful scheme for multilevel metallurgy interconnection, abundant literature has been published on the subject.
References 1, 2 and 3 describe stud formation with the use of metal Reactive Ion Etching (RIE) in chlorine based plasmas. This etching technique requires that an etch barrier which is impenetrable by the etching gas, be used to protect the previously formed metal. Implementing metal RIE is generally not recommended because of the residual contamination caused by chlorine which produces undesired corrosion of metal wires and interconnecting studs.
Reference 4 does not specify an etch stop or the technique used for etching the stud, however the general idea is the same as in the three previously mentioned references. Reference 4 discusses the formation of bumps which will result subsequently in studs. It is to be noted that all the bumps are at the same elevation.
Reference 5 describes the formation of a planarized multilevel metal structure by a process which employs an intermediate blanket silicon nitride layer underneath. Once the silicon nitride layer has been deposited and patterned to expose the first level metal wire at the place where the stud is to be formed, the metal stud is then deposited and lifted off. A second layer of an insulating material, such as quartz or polyimide, is deposited, planarized and etched back to expose the top of the stud.
Reference 6 discloses the use of studs in a multiple metal layer lift-off process but does not deal with the problem of studs of unequal elevation.
Reference 7 solves the problem of studs of unacceptably unequal elevation by the use of a masked etching method which levelizes and insulates the studs for multilevel metal VLSI applications.
During the master slice process some irregularities are created by the nature of certain particular process steps. As a consequence, during the personalization all contacts are not made to the same depth. For example, depending on the particular process, collector regions may be deeper than base regions, and base regions may be deeper than emitter regions.
When the initial wires of the first level of metallization are placed on a substrate, e.g. a patterned silicon substrate to expose desired locations such as device contacts, they conform to its geometry; that is, they must reach into device contacts as well as run across various field oxides covering the silicon substrate. The contacts can be of various depths when compared to the silicon substrate surface. FIG. 1 shows such an irregular surface of a silicon substrate 10 and indicates typical depths of recesses where base and collector device contacts are to be formed. Consider now the formation of vertical wires or studs 11 which are placed on top of corresponding initial wires 12. Said studs will have different elevations depending on whether they are placed in a recess at certain contact locations (e.g. base and collector regions) or on the main surface 13 of the substrate 10. The studs have differences in elevation, although they all have the same height, as it obviously results from the metallization step. Such differences in elevation relative to the most elevated stud are referenced h1 and h2 in FIG. 1. A sequence of steps can be employed using an insulating layer which is then planarized by a thick photoresist and etched back with conditions which will remove unwanted insulator over the metal contacts. Considering the geometries involved, it is obvious that overetching is required during planarization to guarantee that the less elevated contact is exposed. It is furthermore obvious that during this overetch the insulator will be dangerously thinned near the most elevated contact. The most elevated contact will also have surface irregularities caused by the overetch. These surface irregularities cause reliability concerns for metal wiring that must traverse them.
Additionally, it is well known that metal wires, or lands, are not always the exact same size or area. That is, due to power loss considerations, some wires have to be wider than others. Consider now two wires of different sizes 20a and 20b, on the same wiring level 21 of a substrate 22 as shown in FIGS. 2A and 2B. The deposition of the insulating layer 23 is typically a conformal coating. Previous works assumed that the overlying layer 24 of a planarizing medium, such as polyimide or photoresist, will be flat regardless of the underlying geometric shapes. This is not necessarily true. The planarizing material will tend to be thicker over very wide geometries (e.g. 20b) than over very narrow ones (e.g. 20a) as shown in FIG. 2A. Thus, it is obvious that when the surface is planarized in a subsequent etch back step, there will be a residual insulator portion 23b remaining over the wider geometries (e.g. 20b) as is apparent from FIG. 2B.
Therefore, due to substrate surface irregularities and varying metallization widths, the silicon dioxide insulating layer which overlies, for example, the first level of metallization and associated studs, is of non-uniform elevation and thickness. It is therefore necessary to planarize said silicon dioxide layer to render it of uniform elevation, before applying subsequent metallization levels. Because the first level of metallization and studs lie at varying depths below the planarized surface, if all the stud locations were etched simultaneously, undesirable overetch of certain regions of the insulating layer would be required to expose the less elevated studs. More particularly, this overetch would render excessively thin the silicon dioxide in the region of the studs having the highest elevation and their surrounding metallization. This excessively thin insulation would in turn present a danger for low voltage breakdown and an increase in capacitance between the first and second metallization levels. These problems, caused by the irregularities of the substrate surface and by the differences in wire sizes which result in a non-uniform thickness of the insulating layer, have not been seriously investigated up to now, although they appear to be key detractors to a further increase in the number of metal levels.
These problems will be faced by anyone trying to manufacture silicon chips according to the teachings of the aforementioned references. First, elevation of the studs is important when trying to place studs directly on device contacts or when studs are resting at locations (field oxides, device contact regions, resistor regions, Recess Oxide Isolation boundaries, etc.) which are not at the same elevation. Designing a chip to intentionally have similarly elevated studs would force the circuit designer to lower density which is unacceptable. Secondly, studs cannot be of the same size everywhere and distribute the power effectively. Therefore, any process which claims planarity must be able to cope with studs of any size and defines "planarity" in that context. Thirdly, the formation of studs by metal RIE has not been proven as effective, technically or economically, as the lift-off process.